The present invention relates generally to fabrication of integrated circuits, and more particularly, to forming a recess in an interconnect, such as copper interconnect for example, by partially filling an interconnect opening, and to filling the recess with an alloy to form an additional encapsulating material during a thermal anneal on top of the interconnect for preventing material comprising the interconnect from laterally drifting into surrounding insulating material.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and shorted metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to FIG. 1, a cross sectional view is shown of a copper interconnect 102 within a trench 104 formed in an insulating layer 106. The copper interconnect 102 within the insulating layer 106 is formed on a semiconductor substrate 108 such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect 102 is typically formed by etching the trench 104 as an opening within the insulating layer 106, and the trench 104 is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to FIG. 1, the insulating layer 106 is typically comprised of silicon dioxide. Copper may easily diffuse into the insulating layer 106, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material 110 is deposited to surround the copper interconnect 102 within the insulating layer 106 on the sidewalls and the bottom wall of the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material 110 is disposed between the copper interconnect 102 and the insulating layer 106 for preventing diffusion of copper from the copper interconnect 102 to the insulating layer 106 to preserve the integrity of the insulating layer 106.
Further referring to FIG. 1, an encapsulating layer 112 is deposited as a passivation layer to encapsulate the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer 112 is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect 102 does not easily diffuse into such a dielectric of the encapsulating layer 112.
Referring to FIG. 1, in the prior art, the encapsulating layer 112 of silicon nitride is deposited directly onto an exposed surface of the copper interconnect 102 and the surrounding insulating layer 106 after the exposed surface of the copper interconnect 102 and the surrounding insulating layer 106 are polished to a level surface. Unfortunately, the silicon nitride of the encapsulating layer 112 does not bond well to the copper at the exposed surface of the copper interconnect 102. Thus, although copper does not diffuse easily through the encapsulating layer 112 of silicon nitride, copper from the copper interconnect 102 laterally drifts from the interface between the copper interconnect 102 and the encapsulating layer 112 of silicon nitride along the bottom surface 114 of the encapsulating layer 112 of silicon nitride because of the weak bonding of the copper interconnect 102 and the encapsulating layer 112 of silicon nitride.
The copper that laterally drifts from the interface between the copper interconnect 102 and the encapsulating layer 112 of silicon nitride along the bottom surface 114 of the encapsulating layer 112 diffuses into the insulating layer 106 of silicon dioxide to disadvantageously degrade the insulating property of the insulating layer 106. Nevertheless, use of copper metallization is desirable for further scaling down integrated circuit dimensions because of the lower bulk resistivity and the higher electromigration tolerance. Thus, a mechanism is desired for preventing the lateral drift of copper from the copper interconnect 102 along the bottom surface 114 of the encapsulating layer 112 into the insulating layer 106.
Accordingly, in a general aspect of the present invention, an additional encapsulating material is formed on the top surface of the interconnect to prevent lateral drift of conductive material from the interconnect to the surrounding insulating layer.
In one embodiment of the present invention, in a method for filling an interconnect opening to form an interconnect of an integrated circuit, the interconnect opening is formed within an insulating layer. The interconnect opening is partially filled with a conductive material to form a recess within the conductive material toward a top of the interconnect opening, and the recess is disposed within the interconnect opening. An alloy is conformally deposited to fill the recess. Any conductive material and the alloy on the insulating layer are polished away such that the conductive material and the alloy are contained within the interconnect opening.
A thermal anneal is then performed such that the conductive material and the alloy form into a conductive fill of a single grain structure within the interconnect opening. An additional encapsulating material is formed to cover a top surface of the conductive fill during the thermal anneal from the dopant of the alloy diffusing out of the alloy and along the top surface of the conductive fill. A bulk encapsulating layer is formed on top of the additional encapsulating material and on top of the insulating layer.
The dopant metal has a concentration in the alloy that is greater than the solid solubility of the dopant metal in the alloy. For example, the present invention may be used to particular advantage when the conductive material that partially fills the interconnect opening is copper, and when the alloy that fills the recess is a copper alloy with a dopant metal having a solid solubility in copper that is less than 0.1 atomic percent at room temperature. In that case, the dopant metal has a concentration in the copper alloy in a range of from about 0.2 atomic percent to about 5 atomic percent. The additional encapsulating material may be comprised of the dopant metal, or of an intermetallic compound formed from a reaction of the dopant metal with copper, or of a metal oxide formed from a reaction of the dopant metal with oxygen plasma.
In this manner, the additional encapsulating material on the top surface of the conductive fill prevents lateral drift of the conductive material comprising the conductive fill along a bottom surface of the bulk encapsulating layer and into the surrounding insulating layer to preserve the integrity of the surrounding insulating layer.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.